In a media drive, such as a Linear Tape Open (LTO) drive, a self-clocking technique is commonly used for reproducing a phase-synchronized digital signal from a read back signal at a certain sampling frequency. The self-clocking technique generally involves the use of phase-locked loop (PLL) and interpolator (ITR) circuits. For example, in a multi-channel tape drive, each channel has its own PLL to track its phase and frequency errors and generate its own channel bit clock. Generally speaking, the phase error in a multi-channel tape drive contains two main components: (1) phase errors that are unique to individual channels, and (2) a frequency component that is common to all channels. Tracking the error unique to each individual channel allows monitoring of a different phase for each different channel, and tracking the error common to all channels makes all clocks run at approximately the same frequency on average.
Various sources could cause the PLL/ITR circuitry for one or more of the channels to either slip one or more bits, or insert one or more extra bits into the sequence of the phase-synchronized digital signal (also known as “cycle slip”). Inhibiting and/or preventing cycle slip is critical for a reliable and robust media drive because once cycle slip occurs, all of the following code words are incorrectly framed and can thereafter become a long train of uncorrectable errors.
Traditional cycle slip detectors have been implemented in media drives that utilize a single data stream. These types of detectors typically require expensive logics and a relatively long time delay. As technology has advanced, an increasing number of applications have migrated from a single channel media drive to a multiple parallel channel media drive for the transfer of data. For example, over approximately the past decade, the number of parallel channels for many magnetic tape drives has increased from four to eight to 16, with potentially an even greater number coming in the foreseeable future.
In a media drive with multiple inputs and multiple outputs (a MIMO system), there is additional useful information between channels that does not exist in a single channel media drive. When the ITR receives a sequence of erroneous phase and/or frequency information at its input, the numerically controlled oscillator (NCO) block will experience incorrect integration that results in one or more cycle slip events at the bit clock output controlling sampling of the data. Even though the root cause errors are short and within the correction power of a C1 error correction code (ECC), the fact is that they result undesirable cycle slip events. The end result can include a C1 ECC failure due to error propagation.
Fundamental PLL architecture typically includes three major blocks: a Mueller-Miller (MM) phase detector, one or more loop filters, and the NCO. Each of these blocks includes a separate gain. The MM phase detector gain is pattern dependent and can, for example, cover a range from approximately 0.44 to 3.14, in 12T to 2T patterns. In one typical system, nominal loop filter parameters are such that the integral gain is 0.0003, proportional gain is 0.03, and the NCO gain is 1. These numbers can vary based on usage and tuning, however the relative gain differences between blocks are likely to be somewhat similar to these. For example, MM gain will have large and wide variation compared to the loop filter gain(s), and the NCO gain will be larger than the loop filter gain(s). These gains are usually optimized for a steady state loop performance requirement such as bandwidth, phase margin, and gain margin, and assumes that the media drive does not have erroneous input conditions.
When the PLL encounters erroneous transient disturbances, the MM phase detector will typically amplify them. The loop filter integrator will be impacted to a relatively low extent due to very low gains since the function of the loop filter integrator is to track speed variation, rather than phase shift. Therefore, conventional global timing recovery applications which are based on averaging multiple channel loop filter integrators do not effectively or necessarily resolve the problem of cycle slip as described herein. However, the loop filter proportional gain will pass the amplified MM output to the NCO block with some level of attenuation. These transient error events at the input of the NCO block will result in the NCO integrator quickly moving toward an incorrect position and eventually locking into an incorrect phase cycle as the overall PLL loop stabilizes. This move of the NCO integrator to an incorrect position is one of the primary causes of the error propagation event that results in C1 ECC failure.